A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

A high-speed logic gate is attained using new Pb-alloy Josephson IC technology. Three design and fabrication techniques are developed for small I
j
scattering. They are a gate pattern design rule using junctions with identical geometrical construction, a double-layer resist stencil technique, and RF oxidation in CO
2
plasma. A high-gain direct-coupled Josephson logic (HDCL) gate cascade chain is experimentally fabricated using a new 2-µm process developed from this technology. At a high current density of 10 kA/cm
²
, high quality junctions are obtained with a small I
j
scattering of &sigma = 6.8 percent. A very fast switching speed of 4.2 ps/gate is achieved.