Selective epitaxy for CMOS VLSI

Scaling CMOS for VLSI is difficult owing to increasing latchup susceptibility and lateral diffusion of the well which limits packing density. A novel solution to these problems is presented, using selective epitaxial deposition to refill etched wells. In conjunction with a buried-layer implant, a retrograde well profile is achieved with a low sheet resistivity (440 Ω), giving reduced latchup susceptibility. Shallow wells can be used (typically 1 µm) with source/drain-to-well breakdown voltages greater than 9.5 V. Transistor characteristics are good with a long-channel mobility of 192 cm
²
/V.s and subthreshold slope of 100-mV/decade for a 2.5-µm channel length.