A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance R
s
and gate capacitance C
g
, the shallow n
⁺
implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance g
m
, low source resistance R
s
, small gate capacitance C
g
, and small deviation of threshold voltage
\part V_{th}
, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.