A receiver circuit for Josephson computer chip-to-chip logic signal transmissions

A receiver circuit for the transmission of logic signals through package connectors in a Josephson computer is developed. It utilizes new circuit construction. This construction gives operation unaffected by the noise which is induced on the signal transmission paths by high-frequency and high-level ac power current at the connectors. The power current noise reduction ratio at a power frequency of
f
= 250 MHz, which corresponds to a 2-ns machine cycle, is experimentally confirmed to be 0.15.