A trench-isolated submicrometer CMOS technology

A trench-isolation technique is applied to submicrometer CMOS technology to increase packing density and to reduce latchup susceptibility. Device structure considerations and fabrication technology will be discussed. Experimental results of device characteristics using LDD-type NMOS and buried-channel-type PMOS will be presented. The technology is also suitable for fabricating bipolar devices on the same chip.