Resistor-loaded high-speed sense circuit for Josephson memory

A design and experimental verification of a new high-speed sense circuit for Josephson memory are reported. This sense circuit consists of latching logic circuits with resistive loads and is able to adopt
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nonsequential access. It is necessary to decrease base-electrode capacitance of sense gates or to insert dummy inductors in the counter electrodes for the gate in order to realize high-speed memory circuit through word-line impedance matching. In 4-kbit RAM's, it was clarified that the gathering circuit which is composed of two-stage OR gates, each of which is composed of an 8-input wired RCL-OR gate, can minimize the gathering delay time. An experimental sense circuit was fabricated using a 5-µm Pb-alloy process, and the read-out time was measured to be about 400 ps using an on-chip sampling circuit.