A VLSI-suitable Schottky-barrier CMOS process

Trenched Schottky-barrier (TSB) contact PMOS devices for use in latchup-free CMOS are examined in detail, and compared to Schottky-contact PMOS. Measurements and simulations show that the TSB structure has significant advantages in gain and current leakage over the Schottky-contact structure. CMOS using TSB PMOS may be made unconditionally free of latchup. The tradeoffs involving PMOS source-drain implant dose are made explicit and correlated to latchup measurements.