A P-type buried layer for protection against soft errors in high density CMOS static RAMs

A shallow P-type buried layer has been applied to the poly Si load static memory cell in order to suppress α-particle induced soft errors. The effects of the P-type buried layer for suppression of carrier collection due to the funnelling field is verified by a transient 2-carrier 2-dimentional simulator. Various profiles for the buried layer have been tested for CMOS static RAM performances. By means of the optimized process, soft error rate is reduced by three orders of magnitude compared with that of the unprotected structure, and no performance degradation has been observed.