Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p
⁺
-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10
^-7
Ω-cm
²
), and high channel mobility (620 and 210 cm
²
/V . s).