An improved NDRO Josephson quantized loop memory cell with buffering configuration

A Josephson NDRO memory cell operating with all current levels equal has been successfully designed and tested. An additional gate, which acts as a level converter and is called a buffer gate, was employed. As a result, a 0.5-mA equalized operation level with ± 28- percent operating margin was achieved in the design for nominally designed gate parameter. The memory cell design was tested experimentally and current margins
I_{Y'} \geq 0.29
mA,
I_{X} = 0.63
mA ± 22.2 percent,
I_{Y}= 0.60
mA ± 13.9 percent,
I_{S} = 0.62
mA ± 22.8 percent were obtained experimentally. A memory loop inductance L
m
and its ratio
k
were calculated analytically under the conditions of optimum sense discrimination and maximum write tolerances. The memory-loop damping condition was studied by dynamic simulation and two flux quanta storage was successfully achieved and experimentally confirmed. In order to construct memory cell arrays, a novel buffer circuit was proposed and experimentally tested. The memory cell configuration of equalized operating current level contributes to simplifying the design of the peripheral circuits and to improving the operating margin of total random-access memory circuits, including cells and peripherals.