Submicron MOS VLSI process technologies

This paper presents a technical perspective for submicron CMOS VLSI process technology, emphasizing higher packing density and reliability. For megabit level dRAMs, very small cell size below 20 µm
²
with soft-error immunity has been successfully obtained by adopting doped face trench capacitor technology as well as error checking and correcting circuit. For logic LSIs, 0.1 µm thick high quality Si isolated layer on SiO
2
by FIPOS technology, new surface planarization technology using ECR plasma deposition method for trench isolation, gate electrode and multi-level interconnections have been developed. By the submicron process using these technologies, it will be possible to produce 1 Mb or larger dRAMs and several tens kilogate logic LSIs.