Depletion trench capacitor technology for megabit level MOS dRAM

A new technology has been developed for future megabit level MOS dRAM's, in which a depletion-type capacitor is formed at a trench in the cell capacitor region. Trenches have been successfully formed by reactive ion etching utilizing CBrF
3
gas at a pressure of about 14 mTorr. Phosphorous could be doped onto the trench surface with sufficient controllability using a phospho-silicate glass film as a diffusion source. The capacitance of the depletion trench capacitor (DTC) was influenced by the surface orientation of the trench sidewalls. DTC breakdown voltage where gate oxide thickness was 20 nm was more than 7 V. This is large enough for practical use under 3-V operating conditions.