Topography-dependent electrical parameter simulation for VLSI design

A postprocessor for calculating the step crossing resistance and interlayer capacitance from device cross sections from SAMPLE simulation or SEM profiles is presented. An approximate curvilinear square algorithm is used for rapid evaluation of the two-dimensional equivalent number of lateral squares to an accuracy of a few percent. Studies of resistance for single steps and linear gaps are used to determine rules of thumb for resistance dependence on aspect rations, sidewall slope, and facet size. Studies of interlayer capacitance show the importance of reflow shape and the nonscalable sidewall capacitance component. Typical topography effects for today's devices show a fourfold increase in the two-dimensional RC product contribution to signal delay relative to planar structures. New deposition technologies which provide better step coverage are shown to be necessary to improve the scalability of signal delay. A meanderline test structure is used to verify the accuracy of resistance simulation and explore a new bias-sputtering technology.