Influence of a resistive sublayer at the polysilicon/silicon dioxide interface on MOS properties

We suggest that a thin (≥100 Å) resistive sublayer of polysilicon neat the oxide interface can have a pronounced effect on the MOS capacitances-voltage characteristics. On the depletion side of the
C-V
curve, the lower effective work-function difference leads to a higher threshold for strong inversion. On the accumulation side, the MOS capacitance is lowered due to the added thickness of the depletion sublayer. With the help of the sublayer model, we attempt to explain the anomalous behavior often observed in MOS capacitors with silicide/polysilicon gates. The sublayer depletion activates traps due to the heavy impurities (Cu, Fe, and Ta) at the interface, a considerable amount of which were observed in these samples by Auger spectroscopy.