Characterization of CMOS latch-up

The purpose of the work was to characterize the latch-up in an N-well CMOS process with minimum channel length of 1.25
\micro
m. Structures including SCRs, buffers, inverters, and input protections were characterized. Latch-up susceptibility is reduced for P
^-
epi on P
⁺
substrate, starting material of low resistivity, guard band structure, relaxed layout spacings, deeper N-well, and shallower source-drain diffusion.