A pile-up masking technique for the fabrication of sub-half-micron gate length GaAs MESFET's

A pile-up masking technique, using conventional optical lithography and a two-step evaporation process, has been developed to produce sub-half-micron gates of controllable dimensions. The new approach allows a high-yield production of self-aligned and deep-recess gates with multi-layered metallization systems. By using this technique, GaAs single-gate and dual-gate MESFET's with Cr/Au gates 0.2 µm long and 0.9 µm thick (i.e., an aspect-ratio of 4.5) have been fabricated. The technique can be applied to the production of high-frequency low-noise MESFET's.