Fully ion implanted InP junction FET's

This article reports on the fabrication and performance of all ion implanted, 1.0 µm gate length, InP junction field-effect transistors (JFET's). Device fabrication includes the use of multiple energy Si implantation, selective Be implantation, proximity annealing, and Cl
2
plasma etching. The observed 25 V gate-source breakdown voltage is shown, by
C-V
and SIMS analysis, to be a result of a linearly graded junction. At 4 GHz, the maximum insertion gain for these devices was 9.7 dB, while tuning for the optimum noise performance yielded a noise figure of 4.9 dB with an associated gain of 5.8 dB. These results encourage the development of a planar InP JFET technology for use in logic, microwave power, and optoelectronic applications.