Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = t
pd
P
d
) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C
L
= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness X
o
= 450 Å with V
DD
= 3.0 V, to yield t
pd
= 400 ps and P
d
= 250 µW (t
pd
P
d
= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t
pd
and P
d
. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t
pd
describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.