A buried channel/surface channel CMOS IC isolated by an implanted silicon dioxide layer

The design and experimental results for a buried channel/ surface channel CMOS IC isolated by an implanted silicon dioxide layer are presented. A Poisson equation is used in proposing a threshold voltage model for a FET with metal-insulator-semiconductor-insulator-semiconductor (MISIS) structure. Good agreement between measured and calculated threshold voltage versus substrate voltage characteristics is obtained. The propagation delay for an inverter is 0.83 ns, which agrees with that from simulation.