The effect of logic cell configuration, gatelength, and fan-out on the propagation delays of GaAs MESFET logic gates

In this work, three different logic cell configurations, two with and one without a source-follower are employed: These logic cells are arranged in 5- and 11-stage ring oscillator (RO) circuits. The circuits are then fabricated with nominal gatelengths of 0.5, 1.0, 1.5, and 2.0 µm and fan-out loadings of 1, 2, 4, and 8 (consisting of source-gate capacitances). All these test circuits are incorporated into a 6-mm by 6-mm master field. Sufficiently large slices to result in a 4 × 4 array of the master field are used. Si
⁺
implantation into
\langle100\rangle
Cr-doped Bridgman and not intentionally doped liquid encapsulated Czochralski (LEC) substrates have been used with success in terms of reproducibility, long range uniformity, and mobility. Since circuit yields are high, each slice provides a sufficiently large data base for a meaningful statistical analysis to be carried out for each circuit type. These data (propagation delay versus circuit type) together with power dissipation results are presented. Preliminary modeling results of the experimental data are also presented.