Threshold voltage margin of normally-off GaAs MESFET in DCFL circuit

The margin of threshold voltage (V
T
) for GaAs normally-off MESFET DCFL's was numerically analyzed applying the equivalent inverter circuit model. The results show that the optimum (V
T
) is 0.3 V. Quantitative relation between the margin and delay time is obtained as a function of (V
T
). At (V
T
) = 0.3 V, the margin is 0.28 V with t
pd
less than 100 ps for 0.5 µm gate length.