A sub-nanosec, oxide isolated ISL technology

An oxide isolated Integrated Schottky Logic (ISL) gate has been designed and fabricated using 1.25 µm minimum goemetries and a 1 µm thick epitaxy layer. Computer simulations and experimental results show good agreement and demonstrate that this gate structure provides a room temperative gate delay of approximately 0.7ns at a current level of 100 µA.