A dual-gate deep-depletion technique for generation lifetime measurement

A novel, dual-gate deep-depletion effect has been observed in DI/NMOST's (Dielectrically Isolated, n-channel, inversion-mode, MOS transistors). These transistors have a second insulator layer on the bottom, which is electrically accessible by a voltage applied to the semi-insulating polycrystalline silicon substrate, so that the lower insulator forms a second MOS gate. Voltage applied to the lower gate has a transient effect on the upper channel current. This long-time-constant phenomenon (
\tau = 25
s) is similar to that occurring in a deep-depletion capacitor in bulk silicon; however, recovery is limited by the establishment of an accumulation layer on the lower side of the DI silicon layer, rather than an inversion layer on the top surface as in bulk silicon. The effect has been analyzed and used to measure generation lifetime (
\tau_{G} = 20
µs) in the body of the DI/NMOS transistor. This new measurement technique may be applicable to other technologies; in addition, the dual-gate deep-depletion effect may have several device applications.