Quasi-normally-off MESFET logic for high-performance GaAs IC's

The stringent pinchoff voltage control required by the normally-off GaAs FET logic approach appears to be a very serious limitation to its LSI capability. This paper presents the operation and performance of a more tolerant logic IC approach intented to succeed in manufacturing high-performance digital GaAs IC's with LSI complexities. The so-called "quasi-normally-off" MESFET's are utilized, i.e., transistors operating as enhancement-mode devices but having a pinch-off voltage indifferently positive or negative (-0.3 to +0.2 V typically). As well as the genuine normally-off logic, quasi-normally-off digital IC's require a single power supply with a small voltage value (about +3 V). Six alternative circuit configurations, which exhibit different complexity-performance tradeoffs, have been studied by computer simulation. Furthermore, file performance capability of this logic was experimentally tested on 11-stage ring-oscillator circuits fabricated with 1 × 35 µm gate MESFET's. Minimum propagation delays in the range 95-135 ps (depending on the logic gate configuration) and speed-power products of 200-250 fJ (at
V_{DD} = 2.5
V) were achieved. From these results, propagation times in the range 100-200 ps and figures of merit of 50-200 fJ can be expected for logic gates with 10-20-µm FET geometry and LSI-circuit fan-in/loading conditions.