The 3T-CID cell, a memory cell for high-density dynamic RAM's

An experimental and theoretical study of the three-terminal charge-injection device (3T-CID) operating as dynamic memory cell has been made. An optimized cell needs only about 60 percent of silicon surface compared to a classical single-transistor cell having the same storage capacitor. Several experimental arrays with minimum linewidth and spacing of 8 µm have been fabricated using an n-channel Algate LOCOS process with additional steps for the buried layers and contacts to them. The optimal operating voltages and the maximum charge that can be stored are influenced from the punchthrough voltage so that good control of the epitaxial process is necessary. Measurements at various arrays of 32 cells each and different cell sizes with minimum dimensions of 290 µm
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showed sufficiently large bit-line signals, which can be further improved without an important loss of collector efficiency by the reduction of the bit-line width. In memories, however, lateral charge flow along the surface during injection is critical. Measurements showed an improvement if field shield lines and buried drain lines are used.