An improved input protection circuit for C-MOS/SOS arrays

A protective network for silicon-gate C-MOS/SOS arrays has been designed that is capable of protecting input circuits from static discharges in excess of 2200 V. This paper describes the results of a program undertaken at RCA to develop a protection network for C-MOS arrays on sapphire substrates capable of withstanding 1500-v static discharges. A test chip with eight input protection configurations was designed, processed, and tested. The results were incorporated into a network design that exceeds the requirements without degrading circuit speed.