C-MOS/SIS—Using selective SF6etching of {1102} sapphire

A process for selectively etching holes in {1102} sapphire using SF
6
in H
2
is described. SiO
2
, Si
3
N
4
, and combinations thereof are studied as possible etchant masks. Refilling the holes with epitaxial silicon produces an SIS (silicon-in-sapphire) wafer wherein the silicon islands are imbedded into the sapphire substrate. The electrical characteristics of C-MOS/SIS transistors are similar to those of conventionally processed SOS devices.