Excess gate current analysis of junction gate FET's by two- dimensional computer simulation

Gate current in a JFET under high drain bias is much higher than expected from the classical theory for reverse-biased p-n junctions. This excess gate current is caused by minority carriers generated by low-level impact ionization in the conducting channel, while the so-called breakdown voltage is determined by high-level avalanche multiplication near the gate edge at the surface. A simple one-dimensional model for the excess gate current is proposed. This model is based on the results of two-dimensional numerical analysis, which neglects the minority carrier motion. The excess gate current and avalanche breakdown voltage are calculated from one-dimensional ionization integrals, which are obtained numerically by utilizing the solution of two-dimensional analysis. The reverberant effect of the generated carriers on the potential distribution is assumed to be negligible. The results of the calculation are in good agreement with experimental results, without any adjustable parameters. Moreover, various impurity doping profiles are analyzed for the purpose of minimizing excess gate current. The present model requires a reasonably short computation time and is useful for designing JFET devices.