Geometrical factors in avalanche punchthrough erase

It is known that the surface potential of an IGFET can be raised to high levels by reverse-bias pulsing its source and drain. This high surface potential is contingent upon both punchthrough and avalanche injection of majority carriers into the surface region. Erase of some multilayer charge storage memory cells is accomplished using such an avalanche punchthrough erase (APTE) operation. In this paper the maximum surface potential achievable in this manner is assessed for a variety of geometries. The calculation is based upon a Fourier sine transform solution of Poisson's equation, coupled with the sampling theorem for spatially localized functions. The depletion width is determined self-consistently and is found to vary from a minimum value at mid-channel to a maximum value at the channel ends. It is found that the maximum surface potential is achieved for devices whose junction depth is comparable to or greater than the channel length. Under these conditions the surface potential can be as large as the reverse bias less the punchthrough voltage. To avoid serious short-channel behavior during normal read operations, it is suggested that the condition
Nl^{2} > 2V_{D}k\isin_{0}/e
be observed, where
N
= doping level/cm
³
,
l
= half channel length, V
D
= drain voltage during read, K = dielectric constant of semiconductor, ∈
0
= permittivity of free space,
e
= electronic charge. Thus for a 2-µm channel length we recommend a junction depth ≥2 µm, and a doping level ≈6.5 × 10
¹⁵
/cm
³
for a memory cell which is to use APTE and a read voltage
V_{D} \simeq 5
V.