Electrically erasable buried-gate nonvolatile read-only memory

An electrically erasable buried (floating) gate memory is described. The memory is programmed by electron injection by junction avalanche. An internal voltage multiplication scheme using varactor bootstrapping is used which makes nearly 40 V available at the memory cell for programming, yet requires input voltages no higher than 25 V. Erasure takes place by modified Poole-Frenkel conduction in a Si
3
N
4
film of 700-Å thickness which overlays the buried gate. Standard silicon gate p-MOS processing is used with only minor modifications. Memory retention is excellent and is extrapolated to many years even at 150°C. Above 298 K, the time required for the charge to decay to one-half its initial value is given by
\log t_{1/2} = \frac{5254}{T}-\frac{771}{T}√V_{E}(s)
where
T
(K) is the temperature and V
E
is the erase voltage. The endurance of the buried-gate memory is approximately 10 K write-erase cycles and is limited by electron trapping in the insulator. A fully decoded 1024-bit memory chip was designed and fabricated.