Optimum design of power transistor switches

An optimization procedure is developed that completely specifies the one-dimensional design of a double-diffused transistor with only two pieces of input data required--the collector-emitter sustaining voltage and the current gain required when the device is operating in the region of quasi-saturation. A simple but experimentally validated model for predicting h
FE
versus I
C
is also developed and used in the optimization procedure. The analysis is intended to apply mainly to the case of high-voltage high-current switching transistors that have a lightly doped collector. Several design examples are given that illustrate the optimization procedure. In the first example it is shown that the emitter area can be minimized, while simultaneously meeting both the H
FE
and BV
CEO
specifications. This result is of economic significance, since it results in the minimization of die size, and hence die cost. Other examples are given that illustrate various extensions of the procedure.