A VLSI DSP chip for real time iterative deconvolution

The design of a CMOS VLSI chip to perform real-time iterative deconvolution is presented. A bit-level systolic array architecture for convolution, multiplication, and addition is used to implement the circuit. A brief introduction to the iterative deconvolution problem is also given. Simulations done to data have shown that the systolic array portions of the chip will yield satisfactory throughput for millions of iterations per second.<
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