BIST and interconnect testing with boundary scan

The boundary scan architecture provides basic controllable and observable points incorporated on a chip which can be utilized for the chip-in-place type of testing. They can also be put to use in built-in self-testing (BIST) by making the chip capable of generating random test patterns and performing data compression. The goal behind BIST is to increase test speed and to further reduce the external tester complexity. The same test architecture can be utilized to test the interconnect (EXTEST) on a board for shorts, opens, and stuck-ats. During this test, the chip-to-chip interconnect on a board is treated as the device under test and a response-to-stimulus type of test is performed. Also a technique of merging BIST and EXTEST has been developed to save test time and external tester hardware. To do this, the TAP (test access port) controller has to be suitably modified in order to generate necessary control signals.<>