Thermal fatigue in silicon power transistors

In silicon power transistor applications, thermal cycling of the transistor may activate a failure mechanism called thermal fatigue. This phenomenon is caused by the mechanical stresses set up by the differential in the thermal expansions of the various materials used in the assembly and heat sink of the transistor. Thermal fatigue often results in cracking of the silicon pellet or failure at the silicon mounting interface. This paper discusses the two types of interfaces encountered in power-transistor chip mounting. In type I (hard-solder) systems, the stress-strain relationship is treated in the elastic region. In type II (soft-solder) systems, the stress-strain relationship is plastic in that at least one component exhibits material flow. For the type I systems, a method is suggested for calculation of the forces acting at each interface. For type II systems, an empirical approach to predicting the number of cycles to failure is given. Accelerated testing techniques for thermal-fatigue evaluation are suggested, and a method of predicting performance for various mounting systems is given. This method uses an equation of the form
N = A_{0}e^{(\gamma0/H)}
. This paper combines an analytical approach to the design of power transistors with an empirically derived method of predicting failure under conditions of thermal fatigue.