P-I-N isolation for monolithic integrated circuits

A new isolation scheme is described in which the device is fabricated in an intrinsic region isolated from other regions and from the
P^{+}
substrate by a
P-I-N
structure. Thus the component-to-substrate capacitance and the substrate resistance are reduced by one order of magnitude or more, and the coupling or crosstalk is consequently reduced by several orders of magnitude. The fabrication process involves only conventional epitaxy and diffusion techniques. The intrinsic regions are obtained through gold compensation. Compared to
P-N
-junction-isolated gold-doped integrated devices, the
P-I-N
-isolated circuits require only one additional step-a second epitaxial deposition. Preliminary experimental data give
P-I-N
capacitance of about 0.013 pF/mil
²
and breakdown voltage of 200 volts.