High-yield processing for fixed-interconnect large-scale integrated arrays

High-yield manufacturing methods will be essential for future economical fabrication of large-scale integration (LSI) arrays. A progress report is presented on a program aimed at fabricating bipolar LSI arrays directly using fixed, nondiscretionary interconnections among components. Array complexity is to be approximately 10
³
silicon transistor on a chip (100 to 200 high-speed emitter-coupled logic gates). Techniques employed to increase yield on initial array vehicles include 1) use of minimum area devices, 2) noncontact photolithographic methods, 3) redundant processing sequences, and 4) special environmental controls and wafer handling.