Parasitic effects in microelectronic circuits

Since the advent of silicon planar technology, the integrated, monolithic, semiconductor circuit has become a reality. As a result, the use of microelectronic circuits manufactured on a monolithic chip has been rapidly increasing for the past few years. However, the adoption or conversion of standard discrete device semiconductor circuits to the monolithic form has introduced additional parasitic effects into the circuit design. In utilizing the monolithic or single silicon chip for a circuit, it is necessary to isolate circuit elements such as transistors, diodes, resistors, and capacitors from each other. The most commonly used method of obtaining isolation is the utilization of reverse biased junctions. The purpose of this paper will be to enumerate and describe the relative magnitudes of the parasitic effects found in the use of reverse biased diodes as a means of isolating circuit elements. These parasitic effects which are associated with both n-p-n and p-n-p transistor elements can be classified into three general types: dc, ac, and transient. The widely applied n-p-n planar transistor is used as the model element in this paper. The design and process interrelationships which influence and control these parasitic effects will also be discussed. In this analysis, the substrate has been considered as the collector of the parasitic p-n-p transistor. Schematic diagrams of each integrated circuit element are shown in the equivalent monolithic form and in a circuit form with representative parasitics indicated by dashed lines. Analysis will be made of the magnitudes of the dc and ac transient parasitics and some typical values experienced will be indicated. Comparisons of characteristics and parasitics will be drawn between three different processes used in the manufacture of silicon monolithic integrated circuits namely: Process A-Nongold doped, no collector island Process B-Nongold doped, with collector island (buried layer) Process C-Gold doped with collector island (buried layer) The advantages of using gold doping to reduce switching speeds of monolithic diodes connected in a number of ways, is shown in a quantative manner. The reduction in the dc current drain to substrate of the monolithic structure by minimizing the h
FE
of the p-n-p is described. In this paper the elements of integrated monolithic circuits namely resistors, diodes, and transistors, are discussed with typical values shown which are realizable. The effects of different processing techniques on characteristics are enumerated and some precautions in the design of the integrated circuits are recommended.