The minimization of parasitics in integrated circuits by dielectric isolation

A radically new technique for the fabrication of integrated circuits which completely changes microelectronic design is described. In place of the back-biased pn junctions usually used for isolation of devices in a substrate, a dielectric is substituted whose properties are such that almost total isolation is achieved with no increase in area. Leakage currents are reduced by several orders of magnitude to around 10
^-10
amperes/cm
²
, stray capacitances to around 10
^-5
pf/µ
²
, parasitic npnp and pnpn action is eliminated, and breakdown voltage is increased up to 1000 volts. Great flexibility in the design of components is achieved through the ability to place highly conductive "wells" where needed to obtain the benefits of epitaxial techniques, and by the ability to use devices having higher breakdown voltages. The technique makes practically all circuit configurations possible, and greatly enhances the possibilities for fabrication of npn and pnp transistors in the same substrate. Some details on circuits fabricated by this technique are given, such as digital circuits with propagation delay times of 3 nanoseconds and a video amplifier with a gain-bandwidth product of over 700 Mc.