Integrated high speed pin-diode grown by LP-MOVPE on selectively etched substrates

A concept for the integration of a p-i-n diode and a FET that allows for the selective optimization of both devices is presented. The fabrication process for an integrated p-i-n diode is described, and the results obtained with integrated devices are compared to standard p-i-n diodes. This process involves epitaxy for the high electron mobility transistor (HEMT) layers, selective etching of windows for the detector layers, epitaxy for the detector layers on an unmasked wafer, and selective etching of windows for the HEMT. All critical lithographic steps can then be performed on a planar wafer. A cross section of the integrated receiver is shown.<
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