A low noise folded bit-line sensing architecture for multi-Gb DRAM with ultra high density 6F2cell

A new low noise sensing architecture for 6F
²
DRAM cell is presented, employing two noise reduction methods; Divided Sense and Combined Restore Scheme and Noise Absorbing Scheme which eliminate word line to bit line coupling noise and bit line to bit line coupling noise, respectively. The new sensing architecture reduces bit line noise to less than 15% of a conventional scheme with only 0.2% area overhead. The 6F
²
cell enables the giga bit DRAM to have about 85% chip area of conventional DRAM. The measurement results of the fabricated test chip show stable DRAM operations and the proposed sensing scheme is useful in multi-giga bit DRAM.