A self-tuning DVS processor using delay-error detection and correction

In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18/spl mu/m technology. The processor employs delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1 % targeted error rate at a fixed frequency of 120MHz.