A 95mW MPEG2 MP@HL motion estimation processor core for portable high resolution video application

This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video application like an HD camcorder. It features a novel hierarchical algorithm and a low power ring-connected systolic array architecture. It supports the frame/field and bi-directional prediction with half-pel precision for 1920/spl times/1080@30fps resolution video. The search range is /spl plusmn/128/spl times//spl plusmn/64. The ME core integrates 2.25M transistors in 3.1mm/spl times/3.1mm using 0.18micron technology.