Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>10/sup 5/ endurance and good retention at 150/spl deg/C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.