Interfacial stress characterization for stress-induced voiding in Cu/low-k interconnects

Stress-induced voiding (SIV) was studied in the aspects of global and localized stress variation with the change of copper geometries. Two types of interconnect structures were adopted to evaluate resistance shift versus bake time and feature size effect in Cu/low-k systems. A 3D modeling of finite element analysis (FEA) was conducted to profile the stress contour, which directly attributed to the copper voiding underneath via as well as inside via.