Room temperature defect localization of hot and cold failures using scanning probe microscopy techniques

We have developed a defect localization technique at room temperature for devices with nano-leakage and fails only at either cold (0/spl deg/C) or hot (110/spl deg/C) temperature testing using conducting atomic force microscopy (C-AFM) and tunneling atomic force microscope (TUNA). With this technique, we isolated the failure to a single transistor leg (i.e. source, drain, and gate) from two test structures. C-AFM was used to isolate a 90nm CMOS test unit whose failure is stuck at zero "0" logic only at cold and at certain frequency and voltage values. TUNA was used in the second test structure, a flash device that losses charge only at hot temperature. Different sample biases were used to capture and isolate the defect site. I-V curves were obtained on the isolated abnormal contacts to verify the failure models. Defect modeling using Spice simulation was also employed to verify and understand the failure mechanism.