Power minimization for dynamic PLAs

In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus lowering the switching activities in the product lines as well as power consumption. Since there are many candidates for super product lines, we have developed a CAD algorithm based on the maximum weighted matching to find optimal solution. The post simulation results show significant reduction in power consumption. On the average, the power consumption can be saved 58.9% and the delay overhead is merely 1.6% for 18 circuits.