ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD protection zapping test procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical design example in a 0.35/spl mu/m BiCMOS technology.