A background correction technique for timing errors in time-interleaved analog-to-digital converters

A background correction scheme for timing mismatch in time-interleaved analog-to-digital converters (ADCs) is presented. The architecture is based on the use of an extra ADC channel and an input ramp signal to estimate the timing errors, and digital interpolation to correct the output digital codes. Simulated results demonstrate a 35 dB improvement in SFDR (spurious free dynamic range) and a 20 dB improvement in SNDR (signal-to-noise-and-distortion ratio) for a 10-bit converter with an over-sampling ratio greater than 2 times.