On the implementation of 128-pt FFT/IFFT for high-performance WPAN

The paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in the IEEE 802.15.3a standard for wireless personal area networks (WPAN). The 128-pt FFT/IFFT architecture has been designed by devolving it into one 8-pt and one 16-pt FFT. The 16-pt FFT was decomposed again and two separate 128-pt FFT algorithms have been developed, viz., 8/spl times/4/spl times/4 and 8/spl times/2/spl times/8. Their relative merits and demerits have been analyzed from the algorithm and implementation points of view. The architectures have been prototyped on a Virtex II FPGA. The results indicate that the 8/spl times/2/spl times/8 architecture is better suited for the stated purpose.