A 128/spl times/128 floating gate imager with self-adapting fixed pattern noise reduction

We present a novel CMOS current-mode imager that uses nonvolatile floating gate charge storage in the pixel for automatic cancellation of fixed-pattern noise (FPN) caused by fabrication process variations. We demonstrate the ability to reduce the variance of the initial FPN over a range of incident light intensities. Each pixel incorporates a unique circuit that uses pFET hot-electron injection to adapt out the FPN for each pixel in parallel. The design has been fabricated in a commercially available 0.5 /spl mu/m process. Experimental results confirm the ability to reduce the FPN variance by a factor of 98.23 at the intensity at which adaptation was performed, and by a factor of 9.22 over 5 orders of magnitude of intensity. The adaptation takes /spl sim/6 minutes and the 128/spl times/128 image can be read at 7 frames/sec. The chip consumes 43.3 mW.